Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL
The range of new machine learning number formats, combined with the hundreds already present within GPUs has highlighted challenges in specifying, implementing, and verifying numerical hardware. Architects need to explore multiple number formats and precisions, not easily done within standard modelling languages such as C/C++. We present a language, FPCore, that can represent any number format and precision in its purest form and associated simulators capable of comparisons against infinite precision results and exploring multi-precision design spaces. We provide a tool chain that automatically generates a bit accurate C-model from an FPCore representation. Such behavioral models, when converted to RTL, typically exhibit poor power, performance and area. The optimization of such models is beyond current industrial high-level synthesis tool capabilities. We present a tool specifically targeted at optimizing such datapath designs, generating competitive RTL.
Position paper (plarch23-final6.pdf) | 617KiB |
Sat 17 JunDisplayed time zone: Eastern Time (US & Canada) change
16:00 - 17:50 | |||
16:00 15mTalk | Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL PLARCH Theo Drane Intel Corporation, USA, Bill Zorn Intel Corporation, USA, Samuel Coward Imperial College London, UK / Intel Corporation File Attached | ||
16:15 15mTalk | Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design PLARCH Vighnesh Iyer University of California, Berkeley, Borivoje Nikolic University of California, Berkeley File Attached | ||
16:30 10mTalk | New Embedded DSLs for Hardware Design and Verification PLARCH Vighnesh Iyer University of California, Berkeley, Kevin Laeufer UC Berkeley, Young-Jin Park University of California, Berkeley, Rohit Agarwal University of California, Berkeley, Lixiang Yin University of California, Berkeley, Bryan Ngo University of California, Berkeley, Oliver Yu University of California, Berkeley, Koushik Sen University of California at Berkeley, Borivoje Nikolic University of California, Berkeley File Attached | ||
16:40 10mTalk | Fearless Hardware Design PLARCH Rachit Nigam Cornell University | ||
17:00 10mTalk | Library-based Compartmentalisation on CHERI PLARCH | ||
17:10 10mTalk | Non-Newtonian Hardware Design for Longevity PLARCH | ||
17:20 10mTalk | On the Generality of Matrix Multiplication PLARCH | ||
17:30 10mTalk | ChatGPT, Make a Secure Malloc for me PLARCH Pre-print |