PLDI 2023 (series) / PLARCH 2023 (series) / Programming Languages for Architecture /
New Embedded DSLs for Hardware Design and Verification
Over the past few decades, many hardware design languages (e.g. Lava, Chisel, PyMTL3, Amaranth) have been implemented as DSLs embedded in a general-purpose programming language. These HDLs focus on RTL design, but other aspects of hardware design and verification, would be served well with their own specialized DSLs. Taking advantage of functional programming features in a host language, makes creating functional APIs for new eDSLs easy and ergonomic. To show the value of this approach, we demonstrate three new eDSLs, embedded in a functional general-purpose programming language (Scala), specialized for testbench description, stimulus generation, and control flow compilation.
| Position paper (plarch23-final17.pdf) | 477KiB |
Sat 17 JunDisplayed time zone: Eastern Time (US & Canada) change
Sat 17 Jun
Displayed time zone: Eastern Time (US & Canada) change
16:00 - 17:50 | |||
16:00 15mTalk | Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL PLARCH Theo Drane Intel Corporation, USA, Bill Zorn Intel Corporation, USA, Samuel Coward Imperial College London, UK / Intel Corporation File Attached | ||
16:15 15mTalk | Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design PLARCH Vighnesh Iyer University of California, Berkeley, Borivoje Nikolic University of California, Berkeley File Attached | ||
16:30 10mTalk | New Embedded DSLs for Hardware Design and Verification PLARCH Vighnesh Iyer University of California, Berkeley, Kevin Laeufer UC Berkeley, Young-Jin Park University of California, Berkeley, Rohit Agarwal University of California, Berkeley, Lixiang Yin University of California, Berkeley, Bryan Ngo University of California, Berkeley, Oliver Yu University of California, Berkeley, Koushik Sen University of California at Berkeley, Borivoje Nikolic University of California, Berkeley File Attached | ||
16:40 10mTalk | Fearless Hardware Design PLARCH Rachit Nigam Cornell University | ||
17:00 10mTalk | Library-based Compartmentalisation on CHERI PLARCH | ||
17:10 10mTalk | Non-Newtonian Hardware Design for Longevity PLARCH | ||
17:20 10mTalk | On the Generality of Matrix Multiplication PLARCH | ||
17:30 10mTalk | ChatGPT, Make a Secure Malloc for me PLARCH Pre-print | ||
