Sat 17 Jun 2023 17:10 - 17:20 at Magnolia 4 - PLARCH: Session 4 Chair(s): Adrian Sampson

The demise of Moore’s Law has an important implication: the monetary incentive to invest in repeated upgrades for processors will decrease. The understated consequence of this is that processors will need to be designed with the constraint of longevity (and thus fault tolerance) in mind. Architects must design accelerators which maintain performance and increase longevity while not sacrificing too much area or power even in the presence of a broken component.

Traditionally, accelerators have been implemented in a monolithic manner, meaning, if a single part broke, then the whole accelerator becomes unusable. Certainly this is not fault-tolerant. We propose a propose a hardware design methodology for modular accelerators, \textbf{Non-Newtonian Hardware Design} (NNHW), to improve the fault tolerance of accelerators while not overly sacrificing performance or area. We show concrete results for this system built using Cohort. We additionally propose a set of high level requirements for an actor-based software-hardware description language capable of transforming software to hardware when under pressure (like a non-Newtonian fluid’s transition from soft to hard).

Sat 17 Jun

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16:00 - 17:50
PLARCH: Session 4PLARCH at Magnolia 4
Chair(s): Adrian Sampson Cornell University

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16:00
15m
Talk
Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL
PLARCH
Theo Drane Intel Corporation, USA, Bill Zorn Intel Corporation, USA, Samuel Coward Imperial College London, UK / Intel Corporation
File Attached
16:15
15m
Talk
Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design
PLARCH
Vighnesh Iyer University of California, Berkeley, Borivoje Nikolic University of California, Berkeley
File Attached
16:30
10m
Talk
New Embedded DSLs for Hardware Design and Verification
PLARCH
Vighnesh Iyer University of California, Berkeley, Kevin Laeufer UC Berkeley, Young-Jin Park University of California, Berkeley, Rohit Agarwal University of California, Berkeley, Lixiang Yin University of California, Berkeley, Bryan Ngo University of California, Berkeley, Oliver Yu University of California, Berkeley, Koushik Sen University of California at Berkeley, Borivoje Nikolic University of California, Berkeley
File Attached
16:40
10m
Talk
Fearless Hardware Design
PLARCH
Rachit Nigam Cornell University
17:00
10m
Talk
Library-based Compartmentalisation on CHERI
PLARCH
Dapeng Gao University of Cambridge, Robert N. M. Watson University of Cambridge
17:10
10m
Talk
Non-Newtonian Hardware Design for Longevity
PLARCH
Guy Wilks UC Santa Barbara, Jonathan Balkind UC Santa Barbara
17:20
10m
Talk
On the Generality of Matrix Multiplication
PLARCH
Andrew Alex UC Santa Barbara, Zachary Sisco UC Santa Barbara, Jonathan Balkind UC Santa Barbara
17:30
10m
Talk
ChatGPT, Make a Secure Malloc for me
PLARCH
Jeremy Singer University of Glasgow, Zheng Wang University of Leeds, UK
Pre-print