Matrix multiplication is an operation present in many hardware accelerators on many device classes. While several direct applications for this hardware make it useful on its own, we show that it is possible to leverage this hardware to perform general-purpose computation. We present a mapping from a “Turing-complete”, one instruction-set computer and then follow with preliminary work towards mapping to a more realistic RISC-style ISA. We leverage program synthesis to generate the matrix representations of these operations and explain mechanisms that would make this a feasible model of computation given the appropriate hardware.