Sat 17 Jun 2023 10:00 - 10:15 at Magnolia 4 - PLARCH: Session 1 Chair(s): Adam Chlipala

We propose abandoning leakage models for verifying timing properties of cryptographic software, instead directly verifying software with respect to a hardware implementation at the gate level. In early experiments, we verified that a program computing Ed25519 signatures on a 7-stage pipelined processor executes in a constant number of cycles. Significant open challenges remain, including scaling up the tool to modern out-of-order speculative cores and extending the approach to reason about library code outside the context of a whole application.

Sat 17 Jun

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09:00 - 11:00
PLARCH: Session 1PLARCH at Magnolia 4
Chair(s): Adam Chlipala Massachusetts Institute of Technology

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09:00
15m
Talk
Goals for a modern ISA specification
PLARCH
09:25
15m
Talk
Generate Compilers from Hardware Models!
PLARCH
Gus Henry Smith University of Washington, Benjamin Kushigian University of Washington, Vishal Canumalla University of Washington, Andrew Cheung University of Washington, René Just University of Washington, Zachary Tatlock University of Washington
09:40
10m
Talk
Semi-Automated Translation of a Formal ISA Specification to Hardware
PLARCH
Harlan Kringen UC Santa Barbara, Zachary Sisco UC Santa Barbara, Jonathan Balkind UC Santa Barbara, Timothy Sherwood University of California at Santa Barbara, Ben Hardekopf University of California at Santa Barbara
File Attached
10:00
15m
Talk
Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
PLARCH
Anish Athalye MIT, M. Frans Kaashoek Massachusetts Institute of Technology, USA, Nickolai Zeldovich Massachusetts Institute of Technology, USA, Joseph Tassarotti NYU
Pre-print
10:15
15m
Talk
Hardware-Software Codesign for Mitigating Spectre
PLARCH
Nicholas Mosier Stanford University, Kate Eselius Stanford University, Hamed Nemati Stanford University, CISPA Helmholtz Center for Information Security, John C. Mitchell Stanford University, Caroline Trippel Stanford University
File Attached
10:30
15m
Talk
Hardware Verification of Timing Side Channel Freedom in the Spectre Era
PLARCH
Stella Lau MIT CSAIL, Thomas Bourgeat MIT CSAIL, Clément Pit-Claudel EPFL / AWS, Adam Chlipala Massachusetts Institute of Technology