Sat 17 Jun 2023 09:40 - 09:50 at Magnolia 4 - PLARCH: Session 1 Chair(s): Adam Chlipala

Software compiler engineers target ISAs so that compiled machine code can run on a common platform and is correct and as efficient as possible. On the other hand, hardware engineers target ISAs so that their processors can support certain classes of software. This separation of duties is problematic because it deepens the difficulties of verifying correctness from compiled code down to its hardware. We see an opportunity to alleviate these concerns by automating this passage from ISA to hardware. The challenge is that verification and automation tooling for ISAs and hardware description languages (HDLs) have tended to treat implementation effects, such as state, exceptions, and non-determinism, in a variety of different ways, not to mention, these tools can be spread across the imperative/functional language spectrum. By concentrating on tools which originate in the functional programming space, we observe that a simple (unoptimized), functionally correct hardware implementation for a processor may be derived in a straightforward manner from the ISA’s formal specification. We propose a proof of concept for translating formal ISA specifications to valid hardware implementations, e.g. in Verilog, in a single software pipeline.

Position paper (plarch23-final19.pdf)436KiB

Sat 17 Jun

Displayed time zone: Eastern Time (US & Canada) change

09:00 - 11:00
PLARCH: Session 1PLARCH at Magnolia 4
Chair(s): Adam Chlipala Massachusetts Institute of Technology

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09:00
15m
Talk
Goals for a modern ISA specification
PLARCH
09:25
15m
Talk
Generate Compilers from Hardware Models!
PLARCH
Gus Henry Smith University of Washington, Benjamin Kushigian University of Washington, Vishal Canumalla University of Washington, Andrew Cheung University of Washington, René Just University of Washington, Zachary Tatlock University of Washington
09:40
10m
Talk
Semi-Automated Translation of a Formal ISA Specification to Hardware
PLARCH
Harlan Kringen UC Santa Barbara, Zachary Sisco UC Santa Barbara, Jonathan Balkind UC Santa Barbara, Timothy Sherwood University of California at Santa Barbara, Ben Hardekopf University of California at Santa Barbara
File Attached
10:00
15m
Talk
Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
PLARCH
Anish Athalye MIT, M. Frans Kaashoek Massachusetts Institute of Technology, USA, Nickolai Zeldovich Massachusetts Institute of Technology, USA, Joseph Tassarotti NYU
Pre-print
10:15
15m
Talk
Hardware-Software Codesign for Mitigating Spectre
PLARCH
Nicholas Mosier Stanford University, Kate Eselius Stanford University, Hamed Nemati Stanford University, CISPA Helmholtz Center for Information Security, John C. Mitchell Stanford University, Caroline Trippel Stanford University
File Attached
10:30
15m
Talk
Hardware Verification of Timing Side Channel Freedom in the Spectre Era
PLARCH
Stella Lau MIT CSAIL, Thomas Bourgeat MIT CSAIL, Clément Pit-Claudel EPFL, Adam Chlipala Massachusetts Institute of Technology