PLDI 2023 (series) / PLARCH 2023 (series) / Programming Languages for Architecture /
Generate Compilers from Hardware Models!
This program is tentative and subject to change.
Sat 17 Jun 2023 09:25 - 09:40 at Magnolia 4 - PLARCH: Session 1
Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA’s primitives using program synthesis.
This program is tentative and subject to change.
Sat 17 JunDisplayed time zone: Eastern Time (US & Canada) change
Sat 17 Jun
Displayed time zone: Eastern Time (US & Canada) change
09:00 - 11:00 | |||
09:00 15mTalk | Goals for a modern ISA specification PLARCH Alastair Reid Arm Ltd | ||
09:25 15mTalk | Generate Compilers from Hardware Models! PLARCH Gus Henry Smith University of Washington, Benjamin Kushigian University of Washington, Vishal Canumalla University of Washington, Andrew Cheung University of Washington, René Just University of Washington, Zachary Tatlock University of Washington | ||
09:40 10mTalk | Semi-Automated Translation of a Formal ISA Specification to Hardware PLARCH Harlan Kringen UC Santa Barbara, Zachary Sisco UC Santa Barbara, Jonathan Balkind UC Santa Barbara, Timothy Sherwood University of California at Santa Barbara, Ben Hardekopf University of California at Santa Barbara | ||
10:00 15mTalk | Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography PLARCH Anish Athalye MIT, M. Frans Kaashoek Massachusetts Institute of Technology, USA, Nickolai Zeldovich Massachusetts Institute of Technology, USA, Joseph Tassarotti NYU | ||
10:15 15mTalk | Hardware-Software Codesign for Mitigating Spectre PLARCH Nicholas Mosier Stanford University, Kate Eselius Stanford University, Hamed Nemati Stanford University, CISPA Helmholtz Center for Information Security, John C. Mitchell Stanford University, Caroline Trippel Stanford University | ||
10:30 15mTalk | Hardware Verification of Timing Side Channel Freedom in the Spectre Era PLARCH Stella Lau MIT CSAIL, Thomas Bourgeat MIT CSAIL, Clément Pit-Claudel EPFL / AWS, Adam Chlipala Massachusetts Institute of Technology | ||