In hardware accelerator design, High level synthesis (HLS) lowering high level software languages like C and C++ to circuits remains a tempting substitute for hardware description languages (HDLs). Parallelism in HLS, nevertheless, is confined to loop unrolling and pipelining, which are semantically no different from sequential loops. Systems that support multi-threaded libraries for HLS are likely subject to correctness issues due to inconsistency between memory models used by those libraries and the frontend language’s compiler. To mitigate this issue, our work implements the control operator, a language-level barrier, in Calyx, a general-purpose intermediate language for accelerator design. Apart from enhanced articulation for parallelism, the new syntax can also be exploited to deduce finer-grained data live range patterns useful for compiler optimizations like resource sharing.