Domain-Specific Languages (DSLs) are useful for accelerator design, as they provide high-level abstractions in exchange for a more limited application or architectural domain. Calyx is a shared intermediate language for DSL-to-hardware compilers. DSLs target Calyx, before Calyx optimizes the design and lowers it to synthesizable RTL. One optimization is resource sharing, which collapses multiple copies of the same hardware into a single module. We demonstrate resource sharing using techniques traditional to software compilers, such as live-range analysis, dominator analysis, and inlining. This is possible due to Calyx’s software-like control flow and hardware-like structure (i.e., explicit representation of hardware modules).