Integrating Data Layout into Compilers and Code Generators
Data layout is becoming a central ingredient to achieving high performance code. A layout that is organized according to its desired access order can significantly reduce data movement; the computation must be modified accordingly to match data layout order. We present dlcomp, a code generator for tensor contraction computations. It takes as its input a tensor computation in Einstein notation and a data layout description in the sparse polyhedral format. Using a combination of polyhedra scanning and synthesis, it generates code that iterates over the layout of one tensor and matches each nonzero to the corresponding element(s) in other tensors using an optimized find operation. We briefly discuss how this approach can be generalized beyond sparse tensors.
Sun 18 JunDisplayed time zone: Eastern Time (US & Canada) change
09:00 - 11:00 | |||
09:00 5mDay opening | Introduction CTSTA Fredrik Kjolstad Stanford University | ||
09:05 15mTalk | Software and Hardware for Sparse ML CTSTA Fredrik Kjolstad Stanford University | ||
09:20 15mTalk | Integrating Data Layout into Compilers and Code Generators CTSTA Mary Hall University of Utah | ||
09:35 15mTalk | Tackling the challenges of high-performance graph analytics at compiler level CTSTA Gokcen Kestor Pacific Northwest National Laboratory | ||
09:50 10mPanel | Discussion CTSTA | ||
10:00 5mBreak | BreakSocial CTSTA | ||
10:05 15mTalk | Challenges and Opportunities for Sparse Compilers in LLM CTSTA Zihao Ye University of Washington | ||
10:20 15mTalk | The Sparse Abstract Machine CTSTA Olivia Hsu Stanford University | ||
10:35 15mTalk | TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators CTSTA Nandeeka Nayak University of Illinois at Urbana-Champaign | ||
10:50 10mPanel | Discussion CTSTA |