Hardware accelerators have become ubiquitous in modern computer architectures, from Google’s TPU to the dozen different accelerators on the Apple M1 SoC. While domain specific languages (DSLs) offer a productive way of generating efficient hardware accelerators (Aetherling, Dahlia, Reticle), building DSL-to-circuit compilers is an arduous task. This tutorial covers Calyx, an LLVM-like compiler infrastructure for building DSL-to-circuit compilers. We’ll go over building a frontend that compiles to Calyx and uses Calyx to generate and simulate hardware designs. We’ll also show how to implement a compiler pass using Calyx and how to debug Calyx-based frontends using our software-like debugging infrastructure.