Sparse accelerators have traditionally been designed in a largely ad-hoc manner, which makes both comparisons between existing accelerators, and the design space exploration of future accelerators, more difficult. This ad-hoc design process is partly caused by the lack of simple and expressive abstractions that can accurately describe all the different components of sparse accelerator design. To address this need, we introduce a new DSL, called “Stellar,” which accurately describes and decouples (i) the functionality of a sparse accelerator, (ii) the scheduling of operations on it, (iii) the sparse data structures it supports, and (iv) the load-balancing techniques it supports. Stellar enables users to quickly design and explore sparse accelerators, and also generates both Verilog implementations and programming stacks for them.