As hardware design complexity increases due to the end of Moore’s Law and Dennard Scaling, ensuring correctness through rigorous verification is essential as hardware bugs are often impossible to fix post-fabrication. Hardware verification techniques, including formal and dynamic verification tools, face scalability and applicability challenges. In this paper, we propose a novel probabilistic dynamic partial order reduction (PDPOR) method for hardware testing and verification to address the limitations of both formal and dynamic verification approaches. Our method aims to improve the efficiency and effectiveness of hardware verification while addressing issues such as state explosion and compatibility with existing tools.
Tianrui Wei University of California, Berkeley, Shangyin Tan University of California at Berkeley, Koushik Sen University of California at Berkeley, Krste Asanovic University of California Berkeley
